1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a capacitor of a semiconductor device.
2. Description of the Background Art
In various technical fields using integrated circuits, a DRAM (Dynamic Random Access Memory) is widely used for a memory device, and recently, the DRAM is rapidly becoming more highly integrated.
Most DRAM devices are fabricated by using a silicon substrate, and each cell of the DRAM includes a single MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A source of the MOSFET in each cell is connected with a single storage capacitor.
In order to improve the integration of the DRAM cell, each cell area is reduced in size; consequently, storage capacitance is reduced. Reduction of the storage capacitance leads to a reduction of a source/drain ratio and degradation of reliability due to an undesirable signal problem.
Therefore, in order to improve integration without degrading reliability, a capacitor having a sufficient capacitance has to be formed in the reduced cell.
As one approach to improve the capacitance in the DRAM cell, a stacked cylindrical capacitor is used. The cylindrical capacitor has a capacitor structure such that a space on a device is utilized as a capacitor plate to thereby improve capacitance.
The stacked cylindrical capacitor is formed in a manner that, after a hole for forming a lower electrode is formed, polysilicon is deposited to form the lower electrode. Then, the polycrystalline silicon is separated from each lower electrode by etching back or by Chemical Mechanical Polishing (CMP), to form each capacitor. In this respect, the etch back technique is mostly used to prevent a deficiency due to a slurry foreign material produced during the CMP process.
FIGS. 1A through 1G show the processes steps of a method for forming a capacitor in accordance with a conventional art.
First, as shown in FIG. 1A, there is prepared a semiconductor substrate 1 having a MOSFET (not shown). The semiconductor substrate 1 is divided into a cell region (A) and a periphery region (B).
A first insulation layer 3, typically made of silicon oxide, is formed on the upper surface of the semiconductor substrate 1. A hole 5 is formed at a portion corresponding to the cell region (A) of the first insulation layer 3 by the well known photo-etching technique, and a plug 7 is formed in the hole 5.
Subsequently, a second insulation layer 9, made of silicon nitride, is formed on the upper surface the first insulation layer 3 and of the plug 7. And a third insulation layer 11, typically made of silicon oxide, is formed on the upper surface of the second insulation layer 9.
Next, as shown in FIG. 1B, photoresist film is coated on the upper surface of the third insulation layer 11 and patterned to form a photoresist film pattern 13.
And then, predetermined portions of the third insulation layer 11 and of the second insulation layer 9 are etched by an etching process using the photoresist film pattern 13 as a mask to form a hole 15 exposing the plug 7.
At the same time, the regions corresponding to the margin portions of the cell region (A) and of the periphery region (B), forming a line 17 are etched. The line 17 forms a boundary defining the cell region (A) and the periphery region (B) of the semiconductor device.
And, as shown in FIG. 1C, the photoresist film pattern 13 is removed, and a polycrystalline silicon layer 19 is deposited on the upper surface of the third insulation layer 11 and in the hole 15 and in the line 17. The polycrystalline silicon layer will later form a lower electrode.
Then, as shown in FIG. 1D, an oxide film 21, such as an SOG (Spin On Glass) or a USG (Undoped Silica Glass) that has a favorable gap fill characteristic, is deposited on the upper surface of the polycrystalline silicon layer 19 and is etched back to expose the polycrystalline silicon layer 19 formed on the surface of the third insulation layer 11.
Next, as shown in FIG. 1E, the polycrystalline silicon layer 19 positioned on the surface of the third insulation layer 11 is etched to separate the polycrystalline silicon layer 19, forming lower electrode 23. The lower electrode 23 is connected with the plug 7.
And then, as shown in FIG. 1F, a photoresist film pattern 25 is formed on the third insulation layer 11 corresponding to the periphery region (B). The photoresist film pattern 25 serves to prevent the portion corresponding to the periphery region of the third insulation layer 11 from being etched during a follow-up etching process.
Lastly, as shown in FIG. 1G, the portion corresponding to the cell region (A) of the third insulation layer 11 is etched and the photoresist film pattern 25 is removed, thereby completing formation of a capacitor lower electrode.
However, the method for forming the capacitor by etching back in accordance with the conventional art has the following problems.
As the cell becomes small in size, in order to obtain a large capacitance, the lower electrode should be high, for which, thus, the photoresist film 13 has to be sufficiently high for etching the hole 15 for the lower electrode. However, because the cell is reduced in size, the photoresist film is lower in height to obtain the desired pattern by the well known photo-etching technique.
Thus, in order to avoid this problem, before performing the photo-etching, a polycrystalline silicon (not shown) is additionally deposited as a hard mask and then etched.
However, in this case, since the polycrystalline silicon to be etched by the etch back process to separate the lower electrode is increased in thickness, after the polycrystalline silicon is etched back, the upper portion of the lower electrode 23 becomes sharp.
When the upper portion of the lower electrode becomes sharp, electric field collects at the sharp portion, resulting in a high possibility that leakage current occurs.
And, in case that a positive (+) voltage is applied to an upper electrode, since the dopant at the sharp portion is distanced from the dielectric film, a depletion phenomenon occurs, causing a reduced capacitance.
In addition, since a number of holes are formed at the cell region (A), a loading effect occurs that the etching rate of the hard-masking polycrystalline silicon (not shown) existing at the periphery region (B) is lower than that of the polycrystalline silicon of the cell region during etching.
Thus, if over-etching is performed to completely remove the polycrystalline silicon at the periphery region, the height of the lower electrode is lowered, leading to a reduction in capacitance.
Moreover, in order to prevent the polycrystalline silicon in the hole from being etched during the process of separating the lower electrode, the hole has to be filled with the oxide film 21, such as the SOG or the USG having a good gap fill characteristic, and then the oxide is to be removed. This makes the processes complicated.
Furthermore, in order to prevent the increase of the step coverage between the cell region (A) and the periphery region (B), which is caused as the periphery region (B) of the third insulation layer 11 is etched, the photoresist film pattern 25 has to be formed on the surface of the third insulation layer 11 corresponding to the periphery region (B). This also makes the processes complicated.
In addition, the photoresist film pattern 25 has to be formed on the third insulation layer corresponding to the periphery region (B) before the third insulation layer 11 between the lower electrodes 23 is removed by wet etching, and it is not possible to dry the wafer by using IPA (IsoPropyl Alcohol). The reason for this is that, in case that the IPA is used in the presence of the photoresist film, the photoresist film will melt.
Therefore, in the conventional art, wet etching is performed in single wafer type equipment using a spin dry method or in bath type equipment in which the wafer is rotated in the state of box for drying.
In the case of the single wafer type equipment using the spin dry method, in order to etch the oxide film, the etching time per a sheet of wafer is lengthened in proportion to the thickness of the oxide film, causing degradation of throughput.
Meanwhile, in the case of the path type equipment for drying the wafer in the state of box, since the rotation radius is lengthened, its centrifugal force becomes too strong, so that there is a high possibility that the lower electrode is released.
Therefore, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device which is capable of solving problems caused when a lower electrode is separated by etching back.
Another object of the present invention is to provide a method for forming a capacitor of a semiconductor device which is capable of solving problems associated with Chemical Mechanical Polishing (CMP) by removing a slurry foreign material produced when a lower electrode is separated by the CMP.
Still another object of the present invention is to provide a method for forming a capacitor of a semiconductor device which is capable of preventing a periphery region from lowering more than a cell region without using a photoresist film, to thereby reduce process steps and allow use of a bath type wet station of IPA (IsoPropyl Alcohol) vapor drier.
These and other objects are achieved by providing a method for forming a capacitor of a semiconductor device comprising the steps of: forming a first insulation layer on the upper surface of a semiconductor substrate; forming a second insulation layer on the upper surface of the first insulation layer; forming a third insulation layer on the upper surface of the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form at least one hole over a first region of the semiconductor substrate; forming a conductive layer over the semiconductor substrate; performing Chemical Mechanical Polishing (CMP) until an upper surface of the third insulation layer is exposed; and removing portions of the third insulation layer and slurry material from the first region.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.